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Forum Index : Electronics : BMS Revisited

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Warpspeed
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Joined: 09/08/2007
Location: Australia
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Posted: 02:48pm 15 Feb 2020
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I prefer to manually place all my components, then manually run anything that is high voltage, high current, or high frequency, or a bit unusual.
Then let the auto router loose on whatever remains.

I use Protel, and on a big board, something with perhaps 500+ nodes, it does in about one minute what would literally take me at least a very frustrating week to lay out and check manually. Even better still, the electrical and design rule checkers are a huge help in laying out a board that has zero layout errors.

Any other mistakes after that always seem to be due to fundamental design stuff ups by the project idiot.

We have come a very long way from the original tape and doughnuts era.
Cheers,  Tony.
 
Solar Mike
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Joined: 08/02/2015
Location: New Zealand
Posts: 1118
Posted: 02:21am 16 Feb 2020
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  Warpspeed said  ...I use Protel, and on a big board, something with perhaps 500+ nodes, it does in about one minute what would literally take me at least a very frustrating week to lay out and check manually. Even better still, the electrical and design rule checkers are a huge help in laying out a board that has zero layout errors.

Any other mistakes after that always seem to be due to fundamental design stuff ups by the project idiot.

We have come a very long way from the original tape and doughnuts era.



Agree the electrical and design rule checks are great and cut down on mistakes.

Years ago I used use the DOS version of Protel PCB and Schematic, had a dongle card that fitted in a slot inside the PC for activation, still have it, doubt it would run on any PC's today; Probably did several thousand hours of design work using it. Had a windows version Protel 99SE for awhile, but it was a bit of a pain to use, now that Altium has taken its place, I couldn't justify the cost for hobbyist use, so went to DipTrace which had about 1 hr of learning time to get up to speed with it and I find very easy to use; albeit doesn't do some things as well as I would like.

I remember those tape and doughnuts, "Bishop Graphics brand" and a big light table, we used to make the layouts double size, then reduce photographically using a plate camera to 1:1. I had made my own plate camera using the lenses from a photographic enlarger, used to work quite well.

Cheers
Mike
 
Solar Mike
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Posted: 04:31am 22 Feb 2020
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Boards are in the post, 5 days to manufacture, so factory is doing quite well considering.

Mike
 
Solar Mike
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Posted: 10:37am 27 Mar 2020
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PCB's arrived couple of weeks ago, building this project now, to stop going stir crazy, its either that or drink beer, perhaps both, have just bottled 30 x 750cc bottles of dark stout.

Mike
 
Solar Mike
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Posted: 05:33am 28 Jul 2020
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Revisiting this project with version 1.1, similar principle to the old design, but perhaps better operation.

Using the same Opti-Mos dual switches to select each cell in the battery bank, present the cell voltage via a voltage divider to a analog isolation amplifier IC, then to an active filter on the other side of the isolation barrier; CPU can read this voltage directly.

Rather than have modular plugin boards containing the cell dump loads and circuitry, have opted to include this plus a 1 amp load resistor for each cell on the main pcb. The mosfet that switches the load resistance is controlled by an isolation voltage generator chip, similar to previous design, but new chip has a higher output, si8752 and is faster.

Changed the serial constant current LED driver chips to a better design that allows a higher than 5 volt source for the led drive. This ic TLC5925 has a high clock speed and can be connected to the standard CPU high speed SPI serial bus. 16 bits are clocked out per group of 8 cells; when voltages are read the loads are turned off, then clocked back on if required. Have arranged it so the serial bus can be extended in groups of 8 to accommodate bigger cell banks, cells can be 3 to 6 volts.

So the cell addressing will be faster, noting there will be several mSec delay of settling time for each measurement to allow the opti-mos switches change over, them make multiple voltage reads per cell to average out noise.

The system is self calibrating in that a 2.5v reference can be switched in simulating a battery cell, thus CPU ADC count can be adjusted in software to read the correct cell voltage.

Main pcb circuit shown below, minus power supply, no cpu as yet, may place it on a separate pcb with 10pin ribbon cable.









V1.pdf

Cheers
Mike
 
Warpspeed
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Posted: 06:23am 28 Jul 2020
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One potential problem I can foresee placing the discharge loads on the main board.

Before you can measure cell voltage, the discharge load will need to be switched off, if voltage drops in the wiring between each cell and the main board are not going to lead to a significant cell voltage reading error.

That may not be a problem for you, but I discovered pretty early on, that doing cell balancing at the main board, while simultaneously trying to measure each cell voltage accurately produced voltage reading errors that totally confused the whole cell balancing algorithm.

I have had much more success by placing the discharge load directly across the terminals of each cell, then keeping the voltage measurement all high impedance. That way I do not have to cycle the discharge loads off then back on every time I read a cell. That produced much more consistent results.
Cheers,  Tony.
 
Solar Mike
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Posted: 07:00am 28 Jul 2020
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  Warpspeed said  
Before you can measure cell voltage, the discharge load will need to be switched off, if voltage drops in the wiring between each cell and the main board are not going to lead to a significant cell voltage reading error.


Yep, see paragraph that contains wording " when voltages are read the loads are turned off, then clocked back on if required. "


Cheers
Mike
 
Warpspeed
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Posted: 07:52am 28 Jul 2020
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Great stuff Mike.
I have been wrestling with these same problems for a couple of years.

Building a reliable inverter has been very easy in comparison to the whole battery monitoring and battery management issue.
Cheers,  Tony.
 
Solar Mike
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Posted: 09:17am 28 Jul 2020
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  Warpspeed said  Great stuff Mike.
I have been wrestling with these same problems for a couple of years.

Building a reliable inverter has been very easy in comparison to the whole battery monitoring and battery management issue.


Yes it is difficult, I have 3 x 48v banks using 6v lead carbon batteries, 1 x 100v Lifepo4 bank, plus several 12v Lifepo4 banks to monitor; so I want a simple solution that can be quickly setup for this. Its all very well managing your own system, you can keep an eye on things, but when non educated third parties (In battery usage) are involved, any system has to be beyond bullet proof and system messages be in English text on a screen, not a bunch of metering that no one under stands.

Mike
 
poida

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Joined: 02/02/2017
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Posted: 10:35am 28 Jul 2020
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by now the stout is about ready.
need any help dealing with the problem?
(I like stout. ahem..)
wronger than a phone book full of wrong phone numbers
 
nickskethisniks
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Joined: 17/10/2017
Location: Belgium
Posts: 404
Posted: 01:31pm 28 Jul 2020
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  Solar Mike said  

Yes it is difficult, I have 3 x 48v banks using 6v lead carbon batteries, 1 x 100v Lifepo4 bank, plus several 12v Lifepo4 banks to monitor; so I want a simple solution that can be quickly setup for this. Its all very well managing your own system, you can keep an eye on things, but when non educated third parties (In battery usage) are involved, any system has to be beyond bullet proof and system messages be in English text on a screen, not a bunch of metering that no one under stands.

Mike


Yes so true, it needs to be bullet proof and self protected, fool proof!

You can add as many bells and whistles you want, I even tried simple colours...
They need to be read as well...
And ones the system is running like a normal housegrid, there is no one thinking about the system limitations anymore... it's all "normal". Even I'm not allways thinking about the system limits anymore. But I do my "touching" inspection round everytime/day I'm passing by. I hate holiday trips...
 
Solar Mike
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Posted: 10:37am 02 Aug 2020
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First cut of PCB, have allowed for connection to 8 battery cells per module; modules can be daisy chained to accommodate any number to make up the bank.

Cell voltage can be anything really, so any battery type will work, on board resistances for balancing loads of 1 amp per cell; any higher the load resistors can be externally mounted on a heat sink linked by wires.  

Spacing between higher voltage traces currently set at 1.6mm, so should be ok on 100 volt banks.

Will place the analog isolation, filtering etc on another driver pcb with cpu. At some point I want the cpu to send all its data to a large LCD screen (laptop) for ease of monitoring by amateurs, perhaps via a WiFi AT command serial link.

PCB is 267 x 74 mm.





Cheers
Mike
 
Solar Mike
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Posted: 10:39am 10 Aug 2020
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Here is the schematic for the BMS control board, No CPU as yet. Require 15 IO pins, most of the analog is switched by a mux chip, also allows setting up preset values by multi-turn pot, so keyboard not necessary required to get it working.














Cheers
Mike
 
Solar Mike
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Posts: 1118
Posted: 06:12am 20 Aug 2020
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Finally completed a pcb 200x100mm for this project, two types of PSU has been provided for, either a 230vac:12dc for 100v battery systems, or 72:12 for 48v setups.

Ribbon cable output to one or more battery cell sense modules using SPI serial data. Decided to use a Picaxe 20X2 cpu that plugs in on a separate module card, this allows easy way to swap in a different cpu.
Multi-turn pots allow setting of set point voltages, if keypad not used.

Will fire this and the battery cell module design off to be made.

Top:


Bottom:



Cheers
Mike
 
nickskethisniks
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Joined: 17/10/2017
Location: Belgium
Posts: 404
Posted: 07:54pm 20 Aug 2020
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Allways nice to learn from your projects! Thanks for posting your progress, please keep doing that.
Are those uln2003 devices enough protected from the backemf of those relais?
Sometimes I also see relais contact protection with vdr's?
Just some suggestions.
I would like to see some pictures of your finished projects.
 
Warpspeed
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Posted: 10:22pm 20 Aug 2020
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All of those Sprague driver chips (ULN and UDN) are made to drive heavy inductive loads and have internal diodes for back EMF protection.
They are an excellent choice for a project like this.
Cheers,  Tony.
 
Solar Mike
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Posts: 1118
Posted: 01:03am 21 Aug 2020
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  nickskethisniks said  .. Are those uln2003 devices enough protected from the backemf of those relais?


The chips specified with V12 in the part number have mosfet output devices with very little voltage drop when on, so have the internal mosfet diode along with an extra diode on each output common to the +ve supply rail for protection.

As Warp said, they are an excellent choice for driving relays, as they have logic level drive compatible inputs with reasonably high output drive, outputs can be safely paralleled (as done for the fan) to increase the current and take up a lot less pcb space compared to 7 mosfets + gate resistors + extra diodes.

Cheers
Mike
 
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