Guru
Joined: 21/06/2018
Location: AustraliaPosts: 1267
| Posted: 03:12pm 01 May 2021 |
Now I want to buy into the how do we do this best discussion. I define best as, fit for purpose, minimum complexity, low part count, low cost, reliable, easily serviceable, (with a good design hopefully that wont be often) and can be built by a typical home constructor by following the plan and not having access to SMD tools.
I applaud Solar Mike in his approach with separate buffers, that is somewhere between his perfect world scenario and Warps nightmare world. I would like a camp somewhere midway between the two.
Now I ask hopefully a relative question, what are we trying to achieve by presenting a perfectly matched to the nano second on and off command to our paralleled MOSFETs ?
It is relevant here to look at a data sheet, one where they have been brave enough to provide typical switching behaviour of a brand name MOSFET - not many manufacturers give this data and only show a typical value which is almost meaningless to us.
Here is the datasheet FDH055N15A.PDF Now go to page 3 and look at the switching times (which dont state a minimum either) and see that the spread from typical to Max is greater than 1:2 (Poidas 1=2 is starting to look more relevant
). So we got our perfectly matched Gate signals all arriving at the same nanosecond and watch our MOSFETs stuff it up grandly with their different spread of switching behaviour times.If we look at the circuit we are trying to control, it is switching an inductive load, current is (should be) at its lowest level at the turn on event. I would suggest maybe 1 MOSFET could safely handle that at this point, within say 200 nanoseconds all Mosfets should now be shouldering the load on their way to some maximum current & before saturation. Now we turn them off and again within 200nS from fastest to slowest the FETs are now all off. Without doing a heap of maths I reckon that again one FET shouldering that current level for 200nS is probably fine also.
In my opinion, what is critical is having an inductor that will never saturate under any conditions of normal operation, or only saturates softly. Ensure that there is no tendency for Gate bounce (heading for unintended conduction or shoot through)). Ensure there is no tendency for oscillation of the Gate/Drain in any of the bridge quadrants and maybe you have a better chance at a long life.
Although I haven't thrashed my Inverter as much as I would like it appears to be strong and free of any bad tendencies to date.
IF I was tempted to try to improve its performance, I would not change the 1 optocoupler and buffered common gate drive that I used, but perhaps dividing the bridges to 4 x Highside/Lowside Fet nodes that drive 4 smaller chokes that are commoned on their output side. This would force better current matched sinewave signals whilst each pair of MOSFETs shoulders its part of the power without worrying so much about the exact nanosecond timing of all the other pairs - no slow FET then has to shoulder a bulk current, only 25% of it, assuming a 16 FET Power stage.
To save me drawing it out, essentially just imagine a single 4 FET bridge power stage with an output choke. Couple 3 more similar circuits and sum all the choke outputs and we have a much more nicely sharing current scheme ? All of the power quadrants are still driven from the same common opto/buffered gate drives of the original output stage.
I think that's enough for now.... patiently waiting to be shot down in flames.......