Regular Member
Joined: 28/07/2017
Location: AustraliaPosts: 73
| Posted: 12:30am 30 Jan 2023 |
Thanks Peter,
I am using the STM32H743ZIT6 or STM32H743ZIT6U chips with ArmmiteH7V5.50.11 or ArmmiteH7V5.07.00b16
The Chip I am trying to talk with is a MAXQ1061 Cryptographic co processor.
"The MAXQ1061 can act as an SPI slave device. Characters conveyed over the SPI bus are transmitted least-significant bit first, using SPI Mode 0. SPI supports bitrates up to 1Mbps. Clock settings are CPOL=0 (Clock low when inactive), CPHA=0 (Data valid on clock leading edge)"
This is the bitswap algorithm I wrote TxPayload%() MSB in TXData%() LSB out.
for x% = 1 to ByteLength% 'Chip requires LSBit first
TXData%(x%)=0
for y% = 0 to 7
TXData%(x%) = TXData%(x%)<<1
TXData%(x%) = TXData%(x%) or (TxPayload%(x%)<<(63-y%))>>63
next y%
next x%
TXData%(x%)=0
for y% = 0 to 7
TXData%(x%) = TXData%(x%)<<1
TXData%(x%) = TXData%(x%) or (TxPayload%(x%)<<(63-y%))>>63
next y%
next x%
Attached are PDFs of the MOSI + CLK DSO image and MISO + CLK DSO image of the response from the chip.
The chip response is not what is expected.
MAX1061 MOSI + CLK.pdf
MAX1061 MISO + CLK.pdf