SPI device needs LSBit First

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Regular Member

Joined: 28/07/2017
Location: Australia
Posts: 73
Posted: 12:43am 31 Jan 2023      

Hi Peter,

On bytes 2 and 5, why does the MMbasic SPI write function pulse the MOSI high almost immediately after the rise of the 8th clk when the first bit of the next byte is a 0.  If the SPI slave device has any delay after seeing the rising CLK it would incorrectly read the 8th bit as 1 instead of 0.  I would have thought that the MOSI should stay at the logic level of the 8th bit for a short time and then change to the logic level of the first bit of the next byte before the next 8 CLK cycles.

This chips SPI slave is limited to just 1Mhz so it might be a bit slow.
I have tried slower rates of 10kHz, but this probably does not change when this pulsing high of the MOSI line occurs after the 8th CLK.