High idle power revisited

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Joined: 02/02/2017
Location: Australia
Posts: 1400
Posted: 02:45am 07 Sep 2023      

yes, something like that will do the job.
2 channels and external trigger input.

Assuming your gate drive supply is 15V...

set both channels to 5V/div

ch1 is on the low side Gate, the ground clip is on DC supply ground

now, to get the high side Gate signal, we must keep in mind that
this signal rides on top of DC+ supply, potentially 57V
The Gate signal goes from 57V to (57V + 15V)
again, put ch2 ground clip on DC supply ground.

I am lucky to have some isolated probes, which can be used to remove this 57V offset.
But when you don't have these, you need to use the DSO vertical offset to the maximum
to bring the high side Gate signal to the same DC level as the low side.

I see in the Hantec's user manual the offset range is +/- 50V for 0.5V to 10V/div
and so this is just what you need.
Set both channels to 5V/div, use the offset to bring the high side gate down 50V.
Line up both signals vertically and then you will be able to see
the two Gate drive voltages. as the FETs are switched on and off.
This will show if there is much overlap (causing shoot through and high idle loss)

you could have test setups that feed a constant PWM width,
in which case you could just use ch1 to trigger off of.

Or maybe you want to see how it goes for an entire 50Hz output cycle
(approx 400 PWM pulses), so I would use the 50Hz square wave output from the
EG8010 or pico/nano to trigger off, using the external trigger input function.

The DSO has 4M memory when using both channels so it will give you a good view
of what is going on over a long period of (sample) time.