Inverter building using Wiseguys Power board and the Nano drive board

Author	Message
wiseguy Guru Joined: 21/06/2018 Location: Australia Posts: 1156	Posted: 02:30am 10 Mar 2024       Mike is that measured at the gates or the actual rise and fall of the FETs ? I am assuming gates ? Perhaps adding another 50nS would not hurt anything and give a little more breathing space, that looks a bit tighter than expected ? To clarify for others my definition of dead time is roughly the time taken between say the gates of the upper FET turn off and the Lower Fet turn on, and vice versa. But the FETs have a delay and fall and rise time - it is possible for the gate waveforms to look about right but the actual Drains on or off from the conducting state may be quite different causing the "dead time" to actually be reduced. I used 1n5 caps in mine and with the 240R total in series it calculates to ~ 300nSecs. I dont have any screen shots to refer to though and dont remember what it was, I will look again in due course.  Having too much fun with the paperwork