Wiseguy New Inverter Build Nano R6

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wiseguy Guru Joined: 21/06/2018 Location: Australia Posts: 1292	Posted: 09:59pm 18 Jul 2024       The source of the controller PWM opto drives are from TC4424's which are 3 AMP drivers, they are 5V signals.  At first when I considered rebuffering, I would need 5V (more bits) and it was not necessary to re-buffer a 3A signal or even desirable as I wanted to introduce no extra time delays between the 2 stages drive signals. The opto drive FET interrupters look a bit unconventional but their gates are controlled with a 12V drive so if the 5V logic signal is H or L, then the 4 FETs either have 7V or 12V of gate drive with respect to their source so they will be hard on when controlled to be on for their ~13mA gate drive signals with zero delays. When the FETs are controlled to be off, yes there are 2 internal FET diodes both facing upstream so when one FETs body diode could conduct its mating FETs diode opposes the path.   nickskethisniks said   the pwm signals could be buffered again by a 74HC86, the 74HC86 on the controller board  will run close to it's limit I think when powering 2 optodrivers per chanel. The words meaning did not really register to me past the comma - the HC86 if used should have the TC4424 buffer IC loaded, I would not try to drive even 1 power PCB from a lowly 74HC86 drive. By the way for anyone interested, MickeyMouseLogic Edit: The posted schematic appears to have 2 surplus parts. The same node that drives the Gate of Q6 could be connected to the Q1-4 gates, saving D3 and R13. As the logic got simplified I missed it.... Edited 2024-07-19 12:44 by wiseguy