Guru
Joined: 08/02/2015
Location: New ZealandPosts: 1204
| Posted: 11:37pm 10 Apr 2026 |
Ready to test this out, just have to finish making up a new steel framed battery rack with some wheels, so I can easily move it.
Have also got another set of Lifepo4 cells ex EV car, not sure what state they are in, measured a few and seem to be about 85AH, I need to make a rack for these also and do some testing.
I intend to test out a different sort of balancer on these as I want to put them in a small case + balancer + PV charger + LF inverter; not wanting to have too much heat generated by the dissipative balancer resistors, have decided to try out an alternative active balancer setup, similar to a previous project last year.
That previous balancer used multiple forward converters sharing a single ferrite core, one converter per cell, it worked, but with 16 cells started to get a little messy. The large gaps between cell windings on the core did not have enough coupling, too much leakage inductance, creating an inefficient spiky waveform.
So have flipped the design around and gone for a central two switch forward converter powered by the bank voltage 56 volts at balance point, with each cell coupled to the core using a synchronous rectifier. This is similar concept to the design that Warpspeed produced awhile ago.
This new design uses a two mosfet switch forward converter, as this have some advantages over a single switch method; no reset winding is required and less stress on the mosfet switches, disadvantage being it has more components, cost however is similar.
The main primary core has 16 x the number of turns of the secondary cell cores, thus each secondary sees 1/16 of the average bank voltage, high cells (the bank) will place extra charge into lower ones.
Some schematics:
Forward Converter:
Have used "E Diode" opto couplers to drive the 2 mosfets, as this allows good electrical isolation especially with all the RFI generated.
Cell Synchronous Rectifiers:
Near identical to Warpspeeds circuit, have used more modern mosfet drivers that have a under voltage lockout UVLO of 4.5v, so will work with the lower supply voltage generated when the main core switches off:
Synchronous Timing Generator:
The PWM waveform from the CPU goes into this little module, trim pots allow setting the leading and trailing edge dead-times.
Each of the above go on there own separate PCB's and plug into the main motherboard PCB hosting the 16 rectifier modules and ancillary CPU. I have done it this way to keep the individual high current switching contained separated, thus allowing Star grounding of common the 0v rail.
More to come...
Footnote added 2026-04-11 21:16 by Solar Mike
Schematic comments for sync rectifier are wrong, ref parts value have altered.
should say:
forward converter on
Q1 synchronous rectifier is on, cell gets charge:
when off D1 conducts charging C5/6 for V01 power supply.