Senior Member
Joined: 11/11/2021
Location: United StatesPosts: 198
| Posted: 07:14pm 14 Feb 2026 |
Nice captures of the false turn-on waveforms. The most interesting ones to me are the ones under low load conditions where most inverters spend their time when running. My theory is that frequent (PWM frequency) but short false turn-on's under low/no load conditions are pernicious and cause the thin MOSFET gate oxide layer to degrade over time and can eventually fail suddenly even without a significant load.
Looking at the 200W load low-side waveforms of the new board:
200W load, no gate resistor or diode:
200W load, 10R gate resistor and diode:
It looks like the false turn-on peaks (~2.5 to ~3V) are greater than the minimum HY4008/HY5608 gate turn-on threshold voltage (2V). Adding a small gate cap should help reduce the false turn-on peak as it changes the overall Cgd/Cgs ratio. However, it also has other side effects like increased switching loss. Perhaps negative gate bias voltage would be the cleaner way to keep the false turn-on peaks well below the minimum MOSFET gate turn-on threshold voltage.