Y'all ready for this?

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Mixtel90 Guru Joined: 05/10/2019 Location: United Kingdom Posts: 8964	Posted: 07:02am 24 May 2026       It sort of has... From the Datasheet:   Quote   Each Cortex-M33 CPU core is equipped with two instances of a double-precision coprocessor that provides acceleration of double-precision floating point operations including add, subtract, multiply, divide and square root. The design is implemented in just a few thousand gates and so occupies much less silicon die area than a full double-precision floating-point unit. Nevertheless, these coprocessors considerably speed up basic double-precision operations compared to pure software implementations. The coprocessors also offer support for some single-precision operations and conversions. The two coprocessor instances are assigned to the Secure and Non-secure domains. Coprocessor number 4 always maps to the coprocessor used for the current processor security state. Coprocessor number 5 always maps to the Non- secure coprocessor instance, but is accessible only from Secure code. This duplication avoids saving and restoring the coprocessor context during Secure/Non-secure state transitions. Note that there is no speed gain from using integers in BASIC or from a compiler optimising code as integers or single precision. However, where some hardware coprocessors fall back into software mode for double precision the M3 doesn't. These coprocessors are *very* fast  as they are not complex structures.   Quote   Unlike a conventional FPU, the accelerator does not contain a full register bank. Not only does this save die area, it also means that saving and restoring the coprocessor’s state is very fast: in fact, the entire state fits within six 32-bit words and hence can be saved to, or restored from, the CPU in three instructions. The accelerator contains a wide adder, capable of adding two mantissa values and three exponent values simultaneously. There is also a shifter that can either perform a logical right shift by a given amount, or normalise a denormalised mantissa and report the amount of shift required to do so. A considerable amount of hardware in the shifter is shared between these two operating modes. It's pretty impressive really. Section 3.6.2 of the RP2350 Datasheet.