// all 16 bit integer math so it runs fast. This code runs about 300KHz so it's called
// very often so as to get best estimate of rising edge.
u = ADC->ADC_CDR[6]; // fast read of ADC channel 2 on Due
if(psc < 300) // only look for the edge in first 3/4 of 50Hz output
{ // u1, u0 get set to -1 at start of each 50Hz cycle elsewhere
if (u > 1500) // threshold for HI/LOW test of ext sync
u1 = 1;
else
u1 = 0;
if (u1 == 1 && u0 == 0) // we have the transition from low to high now
uedge = REG_PWM_CCNT1; // so record PWM clock source counter
u0 = u1;
}
if(psc == 200) // at end of 1/2 50Hz cycle, check ext sync
{ // to determine leading or lagging phase
if (u > 1500)
{
usign = 1;
}
else
{
usign = -1;
}
}

// this runs once at the beginning of each 50Hz output cycle.
//
burstcount++;
if(burstcount > 3) // only alter the 50Hz period counter once each 4 times
{ // most importantly, the change in the period counter
burstcount=0; // for phase differences is not cumulative
pburst = (uedge - 26250)/4; // PWM period change value, if uedge = 26250 then
} // ext sync is exactly in phase
else
pburst = 0;
u = abs(uedge - 26250);
u2 = u2 - usign*(1+u/256); // need a trim factor for frequency which is cumulative
REG_PWM_CPRDUPD1 = 52500 + u2 + pburst; // update 50Hz PWM period register
REG_PWM_CDTYUPD1 = (52500 + u2 + pburst)/2;
// and maintain 50% duty cycle with new period
REG_PWM_CPRDUPD0 = PPWM + u2/10; // also change 20kHz period reg to suit shorter or longer
// "50Hz" output