Guru
Joined: 02/02/2017
Location: AustraliaPosts: 1432
| Posted: 12:47am 27 Jan 2021 |
Angelo:
I see you experimented with 2x PWM frequency which becomes 40kHz.
It can help some things such as reduce inductor saturation
but it means also 2x switching losses. In our inverter builds switching losses
are not very large to begin with so you and I have scope to experiment.
In the PLL code, which executes once each falling input zero crossing
of the 50Hz input, some calculations are made.
First I get a phase error.
I also get the change in phase error from the prior interrupt.
Next I obtain a correction factor, to be applied to the timer counter
of the 20kHz timer. The correction trims the normally 800 by a small amount
to alter the 20kHz by a small amount, up or down.
The trim factor is
new_delta = 8 * (phase_error / 2 + 8 * (phase_error - old_phase_error));
I could simplify this expression but it allows me to easily try
changes to the expression.
It takes 4 x phase error and 64 x phase error change and this result is
accumulated (or subtracted) into a running total called pcount_delta
This is going to be large number and it will continue to grow larger or smaller
while the PLL is not locked.
pcount_delta is divided by 256, which can be executed fast without a divide instruction
and THIS result is subtracted from the base value of the 20kHz timer count of 800
to yield the new timer count.
The divide by 256 is used to maintain 8 bits of remainder in the division
to carry over better accuracy in the system. It's just factional math and it's
fast.
PLL background:
some PLL designs multiply the lock signal by the system output signal.
You get a cosine (sine x sine = cosine) and then take all but the DC from it and
use the DC to steer the local oscillator into phase lock via a feedback mechanism.
This PLL obtains the phase error directly and infers the two terms needed
for feedback to work (phase and frequency). I produce a feedback correction term
from something like 4 x phase error + 64 x frequency where the units are 8 Mhz clock counts.
The control loop is a simple first order PID.
The proportional component is phase error
The differential component is frequency
There is no integral term.
I can not discuss the PLL workings any more since I lack the mathematical background
required (loop stability, Bode plots, S transforms, etc.)