Guru
Joined: 02/02/2017
Location: AustraliaPosts: 1432
| Posted: 10:05pm 29 Jan 2021 |
Angelo:
feel free to alter the code and try out ideas.
I think it's a fun way to discover and learn.
nano_1_v7_no_bessel_angelo_syncv5.ino.zip
is the result of a couple of days play.
I found I could tune the 50Hz by altering the 20kHz timer,
adding or removing one of the 800 clocks from the timer count.
I now do this in a more sophisticated manner:
for the entire 50Hz cycle, I modify the 800 clock count
adding or subtracting a clock (or not) to give the
required trim. Again I need a bit of fractional integer math.
The guts of the change:
i = pcount_delta/256;
ICR1 = PPWM - i;
pcount_delta = (pcount_delta - 256 * i) + pcount_acc + 135;
// 135 is trim for the 16MHz clock is not quite 16.0000MHz
// the trim puts the PLL loop correction at zero with a 50.0000Hz input signal.
// other wise pcount_acc would = 135 plus any calculated trim.
which occurs at the start of the 20kHz timer 1 overflow interrupt.
The PLL loop produces a value "pcount_acc" and this will increase or decrease
the frequency of the nominal 50Hz. If this = 0, then no change.
pcount_delta just accumulates the trim, and I get the top 8 bits, subtract it
from the 800 clocks, then calculate and leave the low 8 bits in it ready for the next
increment of pcount_acc.
This all permits me to carry 8 bits of accuracy after I do the integer division.
Results are good.
When the PLL is fed a fixed 50Hz to track from the signal generator
the original code is:
+ 50.0039 Hz
- 49.9988 Hz
with a 100uS wide uncertainty of lock position.
The above code gives:
+ 50.0014
+ 50.0003
and 20uS uncertainty
The frequencies are as reported by the DSO on the PLL locked 50 Hz output.
It's input was always 50.0000Hz