Guru
Joined: 02/02/2017
Location: AustraliaPosts: 1483
| Posted: 10:20pm 27 Mar 2017 |
Thanks Mike for the comments.
I am struggling to quantitatively work with the gate capacitance and available current.
I could not get my head around the gate charge/current/time thing. Thanks for the examples. I will look at my prototype and see if it makes sense.
Additionally, when you write
"..In this case the gate resistor should be approx 40 ohms not the normal 5.6, ie 12v/0.267a, to prevent damage to the driver.
With this driver chip if the resistor was made smaller then not all mosfets would turn on evenly as the driver cannot source enough current, so some mosfets will draw more current than others and perhaps self destruct in doing so."
I cant help but think of Tinker's woes.
Maybe a good approach to inverter design would be:
1 select matched FETS, tested as good and well suited for parallel use
2 figure out the gate charge and driver current needed to get sensible switch speeds
3 verify adequate dead time
4 verify ringing on gate or drain or source is small enough to live with
5 ensure little or no dV/dT turn-on, and other parasitic issues
Once these are sorted, only silly overload mistakes should kill the mosfets.
What other failure modes are there?
No 3,4 and 5 will need a decent digital storage oscilloscope.
wronger than a phone book full of wrong phone numbers