Guru
Joined: 02/02/2017
Location: AustraliaPosts: 1440
| Posted: 12:32am 02 Mar 2019 |
Part 26: A closer look at MOSFET gate voltages during switching
In another post on this forum, some interest in shoot through or cross conduction as a failure mode has been shown.
For this discussion, I want to look at one of the 2 half bridges of the MOSFET switched output stage of the inverter. There is no need to examine both of the half bridges, what we see in one of them is reproduced in the other.
Shoot through is defined to be when both the high side and low side MOSFETS conduct at the same time. This is obviously a bad thing, it means the DC supply is conducted through both sides of the half bridge, effectively shorting the DC supply, with current limited by the Rds(on) resistance and DC supply impedance. Some inverters have immense DC supply capacitance and this provides a huge potential current during short circuits.
Reading the specifications of MOSFETS used in these applications, we see something
called Vgs(th) which is the gate voltage, with respect to the Source pin, that is
needed for the MOSFET to show clear signs it is conducting. Not completely conducting, at it's specified Rds(on) resistance, but conducting never the less.
The testing and results that follow are using my test inverter, which uses
IRF3808. I have 4 MOSFETS for each of the 4 legs of the full bridge.
Each leg is fed gate drive that is connected to 4 MOSFETS in parallel.
This is not best practice and risks having one of the 4 switching on a little before the others, and this can be a cause of catastrophic failures. It very probably causes some high frequency oscillation.
The IRF 3800 Vgs(th) is between 2V and 4V
Rds(on) is 5.8 mOhm
Pulsed current max is 550 A, continuous curent is 140A at 25 degC at the junction.
These are reasonable devices for a test inverter.
I want to show the gate voltages (with respect to the low and high side's Source pin)
with the half bridge output voltage. This voltage is measured at the point where we
connect the primary winding of the output transformer.
Yellow is low side gate voltage
Dark Blue is high side gate voltage (with respect to high side Source pin)
Light Blue is the output voltage of the half bridge
It appears I am using only about 10V to switch the gates.
It's clear also the DC supply of the inverter is about 30V as seen in the light Blue
amplitude.
First an overview. To make sense of this, see the upper trace, this shows a bit more than one complete 50Hz output. I am running the current nanoverter code, so it shows clearly the activity of one of the half bridges.
There is a small vertical dark line on the left in the upper trace. This shows where in time the time expanded bottom view is taken from.
Now let's see the low side switch ON event.
We will see the following:
the high side gate go low, with a bit of dead time to allow the...
low side gate go high.
Output voltage drop to zero as the lowside MOSFETS conduct, pulling the output to ground
And what else can we see? The high side gate voltage increase, way past the Vgs(th)
during the rapid drop of the output voltage. You can see it, right in the middle of the lower trace. When I look at the original image I see it peak over 6V.
This is likely resulting in some low power shoot through.
A detail to see, but most importantly, is to observe the low side gate starts to rise
on a slope (defined by gate drive current, gate supply resistance and gate capacitance) until the MOSFET finally conducts fully. This slams the output voltage down to ground rapidly. This fast voltage change, which appears on the high side source pin, as well as the low side drain pin causes the high side gate voltage to rise. Well past threshold voltage. Into conduction. Beyond our control.
I show now the low side switch OFF event.
This is showing what we all think is supposed to happen. We still see some dv/dt induced gate voltage changes. As the output voltage rises rapidly, it causes the high side gate to drop a little, below zero in fact, for a short time.
Looking at the switching at a different time in the 50Hz cycle, we can see some
ugly high frequency oscillations, and shoot through.
As the low side gate is driven low, the dead time permits us to see for a short time
no output voltage, low voltage on both the high side and low side MOSFET gates.
Then it's time to drive the high side MOSFETs ON, pulling the output voltage HIGH.
And all hell breaks loose. As soon as the output voltage rises quickly, the lowside gate is now rising well past threshold and conducts.
I want to make it very clear: The low side gate is no longer under control of the gate drive IC's output. It is being pulled low by the drive IC, via a 4.7R resistor but voltages arising within the low side MOSFET is causing their gates to rise up
well past threshold values. These gate voltages also appear on the drive IC output pins, to a certain extent as well. This is another issue to explore.
This clearly is not a smooth event, the low side gate is oscillating up and down, pulling the output voltage every which way and causing further dv/dt induced changes.
I have attached a current sensor to the DC supply in the past and clear spikes in DC supply current occur during these frenzied switching events from the shoot through.
Notice the output voltage only rises after the high side gate has been charged up enough, into it's fully enhanced conduction stage.
These captures are really very nice, and show the gate voltages just as illustrated in the textbooks (and other publications)
Finally, we see the high side switch OFF event, at this location in the output waveform. Again we can see more dv/dt induced gate voltage change.
The high side gate is pulled low, first a pause as we discharge the capacitor present on the gate, in the chips, then it drops to a value to permit the conduction to stop.
I want to explore further gate voltage behavior in SPWM inverters.
I have one of Madness's power boards, which use beefy transistor based totem pole drives for both low and high side gates. I suspect this approach (totem pole drive) will give a much lower impedence drive to the gates, potentially reducing shoot through. It will almost certainly isolate the gate drive IC output stages from undesirable dv/dt induced voltages coming from the MOSFET gates.
The IR2110 has specifications that clearly state that we must never let their outputs
go below -0.3V compared with ground(low side Source voltage) or VS (the high side Source voltage).
I fit TVS protection to my inverters, protecting the drive IC outputs ONLY.
With a totem pole drive, maybe we will get 2, much needed benefits.
I need to find the time to build Mad's board and then we can find out.
A deep understanding of these switching events is needed, in my view, for us all
to make continued progress in our building and use of home made inverters.
wronger than a phone book full of wrong phone numbers