You are a pioneer with this. I have wondered if doing this would be a complete solution to the induced gate voltages. I am keen to see how you go with this. The timing for those switches will need to be closely coordinated with the main MOSFET gate signalling.
I wonder if dv/dt induced gate voltages when clamped by the extra FETs will still be present within the main bridge MOSFETs and so we still see shoot through... That is, pulling down the Gate to Source is never enough.wronger than a phone book full of wrong phone numbers