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Forum Index : Microcontroller and PC projects : PIO and RP2040 V6.01.00 and PIO READ/WRITE Questions
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homa Guru  Joined: 05/11/2021 Location: GermanyPosts: 523 |
I'm trying my hand at PIOs and mmBasic again. Unfortunately, the responses are not as expected. I'm using an rp2040, i.e., Pi Pico. Thanks @Volhout for the tips so far. Especially regarding the difference between 2350 and 2040 and the new commands. Shouldn't the interrupt trigger here? My test program: > option list PicoMite MMBasic RP2040 V6.01.00 OPTION COLOURCODE ON OPTION CONTINUATION LINES ON OPTION CPUSPEED (KHz) 200000 OPTION DISPLAY 40, 80 > 'PIO TEST FIFO Option explicit Dim pio_0_FSTAT% = &h50200000 + &h4 'PIO0 Register Offset + Register FSTAT Dim integer fifoR(3), fifoW(3) Dim integer ffR, ffW, tmp Array Set 0,fifoR() Array Set 0,fifoW() ffW=0 ' PIO clear 0 PIO ASSEMBLE 0,".program bsp1" PIO ASSEMBLE 0,".wrap target" PIO ASSEMBLE 0, "pull block" PIO ASSEMBLE 0, "mov isr, osr" PIO ASSEMBLE 0, "push block" PIO ASSEMBLE 0,".wrap" PIO ASSEMBLE 0,".end program list" ' PIO CONFIGURE 0,0,10000,,,,,,,,,,,,,Pio(.wrap target),Pio(.wrap) PIO interrupt 0,0,pRX,pTX PIO START 0,0 'PIO interrupt 0,0,pRX,pTX ' Print "pause 1sec" Pause 1000 ' 'TEST FIFO ' 1. read Print "FSTAT: ";Bin$(Peek(word pio_0_FSTAT%),32) PIO READ 0,0,4,fifoR() Math V_PRINT fifoR(), hex ' 2. write Print "Schreiben" Print "FSTAT: ";Bin$(Peek(word pio_0_FSTAT%),32) PIO write 0,0,4,&h1,&h2,&h3,&h4 Pause 10 Print "FSTAT: ";Bin$(Peek(word pio_0_FSTAT%),32) Pause 10 ' 3. read again - interrupt? pRX Pause 10 Print "FSTAT: ";Bin$(Peek(word pio_0_FSTAT%),32) Do Loop Sub pRX Print "Pio FiFo RX" Array Set 0,fifoR() PIO READ 0,0,4,fifoR() Math V_PRINT fifoR(), hex Print "Pio Fifo RX - END" End Sub Sub pTX Print "Pio FiFo TX / TX - End" End Sub And the outputs (1. directly after startup | 2. after Ctrl-C and RUN): PicoMite MMBasic RP2040 V6.01.00 Copyright 2011-2025 Geoff Graham Copyright 2016-2025 Peter Mather > run <---- 1x 0: 80A0 1: A0C7 2: 8020 pause 1sec FSTAT: 00001111000000000000111100000000 EA0A9814, EA0A9814, EA0A9814, EA0A9814 Schreiben FSTAT: 00001111000000000000111100000000 FSTAT: 00001111000000000000111000000001 Pio FiFo RX 1, 2, 3, 4 Pio Fifo RX - ENDE FSTAT: 00001111000000000000111100000000 > run <---- 2x 0: 80A0 1: A0C7 2: 8020 pause 1sec FSTAT: 00001111000000000000111100000000 1, 1, 1, 1 Schreiben FSTAT: 00001111000000000000111100000000 FSTAT: 00001111000000000000111000000001 Pio FiFo RX 1, 2, 3, 4 Pio Fifo RX - ENDE FSTAT: 00001111000000000000111100000000 FSTAT explanation from the rp2040-manual: 00001110000000010000111000000001 ^ ^ ^ ^ | | | 3:0 RXFULL: State machine RX FIFO is full | | 11:8 RXEMPTY: State machine RX FIFO is empty | 19:16 TXFULL: State machine TX FIFO is full 27:24 TXEMPTY: State machine TX FIFO is empty I'm just trying to write data to the TX-Fifo/OSR, PIO reads it WORD and writes it directly back to the ISR/RX-FIFO. My expectation is that the interrupt should trigger. If there is nothing in the RX-FIFO, any values/garbage are okay. But a PIO CLEAR does not reset it either?! After the first start, Ctrl-C, and restart, the 1 always appears (i.e., the last value from the shift-in?!) Only a reset instead of the PIO CLEAR brings back the initial values. Should a PIO READ return nothing/no values if the FIFO is empty (e.g., -1 to distinguish it from 0)? Why is there no interrupt? Can anyone point me in the right direction? I feel like I'm on the wrong track. Matthias Edited 2026-01-03 02:13 by homa |
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| Volhout Guru Joined: 05/03/2018 Location: NetherlandsPosts: 5578 |
I have to check how the interrupt works, or not. Maybe you have to set fifo thresholds before the interrupt happens. I am not used to PIO CONFIGURE, always used PIO INIT MACHINE. But I can Tell you that PIO read (mmbasic side) always returns, even when there is no data in Fifo. It returns with the last value from fifo. You dont want mmbasic to stall if fifo is empty. That is why you can read 5 valies from a 4 deep fifo. It Will always return the most recent value as 5th. The 4th in fifo, or the one being pushed while MMBasic empties the 4. PIO CLEAR N should clear FIFO’s Volhout Edited 2026-01-03 04:02 by Volhout PicomiteVGA PETSCII ROBOTS |
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| Volhout Guru Joined: 05/03/2018 Location: NetherlandsPosts: 5578 |
Just reading the user manual on pio interrupt TX interrupt only happens when TX FIFO is full. When you push 4 values, and have a PIO state machine "waiting" (PULL BLOCK) the first value will be pulled before you write the 4'th into FIFO. So the TX interrupt will never happen. FIFO is never full. You can try this by stopping the PIO, and pushing 4 values in fifo. Then you should get an interrupt. RX interrupt will be set with every single value written in FIFO by the state machine. So not at 4 values, but at every single value. And when you read it, the interrupt will clear, and be set again at the next value. I have not tried it, but may be able to help further sunday next. Not at home at this moment. Volhout Edited 2026-01-03 04:29 by Volhout PicomiteVGA PETSCII ROBOTS |
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| homa Guru Joined: 05/11/2021 Location: GermanyPosts: 523 |
-- I tried 1/7/31 as a parameter and think that is only for parameters /v or /w. t/ pushthreshold (1..31 bits shifted IN in ISR before autoPUSH) u/ pullthreshold (1..31 bits are shifted OUT from OSR before autoPULL) v/ autopush (1 = allow autmatic push) w/ autopull (1 = allow automatic pull) Unfortunately, the information in the manual is sometimes very sparse and scattered in various places :-( I think I'll write a summary when I'm done here! -- Yes, that makes sense, and I can also check it with Pio(FLEVEL 0) or Pio(FLEVEL 0, 0, RX)  -- Based on my observations, unfortunately no. -- understood -- Unfortunately, that won't happen either. I tried that too: PIO ASSEMBLE 0, "set x, 0" PIO ASSEMBLE 0, "mov x, osr" PIO ASSEMBLE 0, "push block" -- No problem, I appreciate the help and food for thought. Matthias |
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| homa Guru Joined: 05/11/2021 Location: GermanyPosts: 523 |
That's all on the topic of PIO INTERRUPT page 155 and page 218 in the examples: PIO INTERRUPT pio, sm [,RXinterrupt] [,TXinterrupt] Sets Basic interrupts for PIO activity. Use the value 0 for RXinterrupt or TXinterrupt to disable an interrupt. Omit values not needed. The RX interrupt triggers whenever a word has been "pushed" by the PIO code into the specified FIFO. The data MUST be read in the interrupt to clear it. The TX interrupt triggers whenever the specified FIFO has been FULL and the PIO code has now "pulled" it PIO CLEAR clears all the PIO FIFO's, as does PIO START and PIO INIT MACHINE. The MMBAsic program doesn't need to wait for data in the FIFO to appear since the RX FIFO can be assigned an interrupt. The MMBasic interrupt routine can fetch the data from the FIFO. Similar for TX interrupt in which case MMBasic gets an interrupt when data is needed for the TX FIFO. PIO INTERRUPT a,b,c,d a/ PIO (0,1 or 2(2350 only)) b/ state machine (0...3) c/ Name of RX interrupt handler (i.e. "myRX_Interrupt" or 0 to disable) d/ Name of TX interrupt handler (i.e. "myTX_Interrupt" or 0 to disable) And this is completely independent of the PIO DMA, right? Edited 2026-01-03 08:17 by homa |
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| Volhout Guru Joined: 05/03/2018 Location: NetherlandsPosts: 5578 |
Homa, I think there is a bug in the RX interrupt. See my post in the 6.01.00 release thread. Volhout PicomiteVGA PETSCII ROBOTS |
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