 Notice. New forum software under development. It's going to miss a few functions and look a bit ugly for a while, but I'm working on it full time now as the old forum was too unstable. Couple days, all good. If you notice any issues, please contact me. |
Forum Index : Microcontroller and PC projects : CMM2: v5.05.04RC7 - RAM and FLASH flexibility
  Page 2 of 3   |
|||||
| Author | Message | ||||
TassyJim Guru  Joined: 07/08/2011 Location: AustraliaPosts: 6283 |
There is nothing to run so you can't have AUTORUN ON and OPTION RAM at the same time. (The OPTION AUTORUN ON gets remembered but does nothing) Autoexec.bas or equivalent is not available either. Jim VK7JH MMedit |
||||
| GregZone Senior Member  Joined: 22/05/2020 Location: New ZealandPosts: 114 |
Note that these SoC's have Harvard Architecture cores (ie. seperated Instruction and Data buses). Typically, these systems allocate SRAM (or the majority of it) to Data storage, with the FLASH memory for Instruction execution. I believe in the STM32H743IIT6, only 64K of the SRAM is actually allocated to ITCM (Instruction RAM). nb. ITM = fast "Tightly Coupled Memory". So, in summary, actual executing machine code must reside in Instruction memory (eg. the FLASH memory), which runs the code that then accesses the Data memory (which includes most of the SRAM). Remember that an interpreted BASIC program is just Data! (The BASIC Interpreter is the firmware Instruction code that is just reading the BASIC "program" as Data). I understand CSUB is implemented as a block of pre-compiled code (ie. the actual "to be executed" machine code output of the external C compiler). Therefore, the CSUB block of code itself needs to reside in the core's Instruction memory. Hopefully I've described that in an understandable way, and my understanding of CSUB implmentation is correct?  |
||||
| matherp Guru Joined: 11/12/2012 Location: United KingdomPosts: 10315 |
Amost completely wrong I'm afraid but you did inadvertently solved the CSUB RAM issue  V5.05.04RC9 http://geoffg.net/Downloads/Maximite/CMM2_Beta.zip Instructions can be in any type of memory. The ITCM memory is just an area that can give fast access to instructions although because of caching the advantages are fairly small compared to using any other type of memory. However, your post triggered me to remember that, for efficiency reasons, I had used the memory mamangement controller to disable instruction access to the SDRAM. By enabling instruction access to the area of SDRAM used for program storage when using OPTION RAM CSUBs now work. |
||||
| GregZone Senior Member Joined: 22/05/2020 Location: New ZealandPosts: 114 |
Thanks Peter. A bit harsh, but I'll certainly concede, given I've not actually coded for any STM32's. However, what I describe is correct for other Harvard Architecture MCU's. I did of course completely overlook the external SDRAM, and was only thinking internal SRAM memory. But, I'm very glad to hear that my input at least triggered a helpful thought!  |
||||
| matherp Guru Joined: 11/12/2012 Location: United KingdomPosts: 10315 |
Your statement about two busses is correct but both buses can access all RAM and FLASH memory. In addition you have DMA access and, in the case of the STM32H7, LTDC access (graphics). All memory areas can be set as data, instruction or shared access using the memory controller. Default is everything but there are performance advantages for locking things down. Add to this separate instruction and data caches and things get even more complex as DMA does not respect caching except in certain memory areas. |
||||
thwill Guru Joined: 16/09/2019 Location: United KingdomPosts: 4311 |
LOL, and it was so convincing that I had follow up questions for my own education. I still have a couple, perhaps answers for them are in the documentation and if so I apologise for not having found them: The micro-controller has 2 MB flash, am I correct in that 1 MB is allocated for the firmware (which you aren't using up entirely) and that by default the lower half of the other MB is for the tokenised program ? The micro-controller also has 1 MB RAM internally and the waveshare adds an additional 8 MB SDRAM. 512K of the internal + 3 MB of the external RAM is allocated to the video. 5 MB (presumably all external) is allocated to variable memory. So what is the last 512K of internal memory used for ? This is your problem Peter, you are just to good. You tell us something can't be done and usually 48 hrs later with minimal fanfare you've done it! It's a reverse Peter and the Wolf situation. I'm not asking for this only educating myself, couldn't rudimentary flash wear leveling be implemented by simply randomising the start address that the tokenised program is written to each time ? Sounds like Jim's experimental work (than you Jim) may prove this all even less necessary than was already being argued. Thank you once again, Tom MMBasic for Linux, Game*Mite, CMM2 Welcome Tape, Creaky old text adventures |
||||
| GregZone Senior Member Joined: 22/05/2020 Location: New ZealandPosts: 114 |
Thanks for summarising Peter. Certainly an impressive chip! These devices just keep adding capabilities (and complexity), making it pretty hard to keep up with what the multitude of currently available devices offer!  |
||||
| matherp Guru Joined: 11/12/2012 Location: United KingdomPosts: 10315 |
No because in order to change flash usage I need to restart the firmware to re-allocate memory usage 64K is instruction memory, various critical flash areas such as interrupt routines are copied into this at reset (ITCM) 64K is for MMBasic simple variables 128K for C stack, heap, variables and buffers (DTCM) 256K for strings, MMBasic temporary memory and MMBasic audio buffers. The MMbasic firmware is in the first 1MB of flash The MMBasic program is in the 2nd 1MB of flash |
||||
| thwill Guru Joined: 16/09/2019 Location: United KingdomPosts: 4311 |
Thank you Peter, And this restart explains why this doesn't run to completion for me: > list "config.bas" option f11 "chdir " + chr$(34) + "/zmim/src" + chr$(34) + chr$(13) + chr$(10) option f12 "chdir " + chr$(34) + "/mbt/src" + chr$(34) + chr$(13) + chr$(10) option search path "/bin/" option ram option sd timing fast option list It looks like changing the SD TIMING also requires a restart? Of course, I had quite overlooked the need for some working memory for the interpreter. Best wishes, Tom Edited 2020-07-24 20:40 by thwill MMBasic for Linux, Game*Mite, CMM2 Welcome Tape, Creaky old text adventures |
||||
| matherp Guru Joined: 11/12/2012 Location: United KingdomPosts: 10315 |
Most permanent OPTIONS require a restart - same as all MM Edited 2020-07-24 21:03 by matherp |
||||
| thwill Guru Joined: 16/09/2019 Location: United KingdomPosts: 4311 |
I'm sorry Peter, I'm obviously being slow. The manual documents OPTION F11 & F12 as being "Permanent", but they take effect immediately and don't seem to require a restart. Whereas is looks like OPTION FLASH|RAM and OPTION SD TIMING actually perform an immediate restart (hence my config.bas not completing) - the red LED flashes, but the MMBasic (c) message is not output ... or at least not visible in my serial connection ? Regards, Tom MMBasic for Linux, Game*Mite, CMM2 Welcome Tape, Creaky old text adventures |
||||
| matherp Guru Joined: 11/12/2012 Location: United KingdomPosts: 10315 |
Most permanent OPTIONS require a restart - same as all MM |
||||
| thwill Guru Joined: 16/09/2019 Location: United KingdomPosts: 4311 |
Editing the history (All -> Most) whilst I'm replying is cheating  Thank you, Tom MMBasic for Linux, Game*Mite, CMM2 Welcome Tape, Creaky old text adventures |
||||
| matherp Guru Joined: 11/12/2012 Location: United KingdomPosts: 10315 |
V5.05.04RC10 http://geoffg.net/Downloads/Maximite/CMM2_Beta.zip When OPTION AUTORUN ON is set with OPTION RAM then the firmware will look for the file AUTORUN.BAS on reset or power up and execute it if found |
||||
| PCG68 Newbie  Joined: 14/07/2018 Location: ItalyPosts: 16 |
V5.05.04RC10 Peter You are great. thanks Jim for the reply. |
||||
| thwill Guru Joined: 16/09/2019 Location: United KingdomPosts: 4311 |
Not that there was any doubt but I can confirm this works ... doesn't help me with my option resetting problem though ... not a big deal, but would like to understand. Regards, Tom MMBasic for Linux, Game*Mite, CMM2 Welcome Tape, Creaky old text adventures |
||||
| matherp Guru Joined: 11/12/2012 Location: United KingdomPosts: 10315 |
saveandreset: // used for options that require the cpu to be reset SaveOptions(1); _excep_code = RESTART_NOAUTORUN; while(ConsoleTxBufTail != ConsoleTxBufHead); MM_Delay(10); SoftReset(); // this will restart the processor Option change deliberately blocks autorun - same for all MM |
||||
| thwill Guru Joined: 16/09/2019 Location: United KingdomPosts: 4311 |
Fair enough. And even if there were a way to cause a full reset from BASIC it wouldn't help me. It's not a big deal, I just need to choose which of OPTION RAM and OPTION SD TIMING FAST I should postpone until the next reboot. Regards, Tom MMBasic for Linux, Game*Mite, CMM2 Welcome Tape, Creaky old text adventures |
||||
| mclout999 Guru Joined: 05/07/2020 Location: United StatesPosts: 490 |
OMG you guys are amazinly responsive to input on this project. I have never seen this level from any project I have gotten involved with. Thanks so much for the work you do. I was involoved with the Commander X16 project but was even snubbed for even bringing up a discussion of the porject and they would just delete your thread without notice even though it may have been a livly discussion. It also is a very underpowered old school 6502 and not much optimized and enhanced like the Sinclar Spectrum Next witch is a good project but absolutely limited because they only had a single run of the hardware. Nice to look at but NO ONE can get one(though there emulator dose completely replicate there system. This is not a dig at all. I know you have a lot on your plat and a more focuse goal that you are hiting out of the park). This project is Accessible affordable powerful and the hardware is available (build your one form Gerber file on up, or from manufacturers actively building them). You guys ROCK are amazingly responsive at maintaining and enhancing the experience of the community. Once again Thank you. I can't wait to get mine but international shipping is turning out to be RATHER FRUSTRATING! Have a great day. Comeing here to the forum make mine. Edited 2020-07-25 01:00 by mclout999 |
||||
| lizby Guru Joined: 17/05/2016 Location: United StatesPosts: 3378 |
What he said. It's very gratifying to see the broad range of experienced techies that the CMM2 has freshly brought to the MMBasic tribe, and Peter's very responsive approach to suggestions which may seem a bit beyond the pale to old-timers has been impressive. Looking forward to learning from all the new inputs. PicoMite, Armmite F4, SensorKits, MMBasic Hardware, Games, etc. on fruitoftheshed |
||||
| Page 2 of 3 |
|||||
 Print this page |
 |
The Back Shed's forum code is written, and hosted, in Australia. | © JAQ Software 2025 |
