void TIM1_CC_IRQHandler(void)
{
   if(valid) DMA1_Stream5->CR |= DMA_SxCR_EN;   // start the DMA
   TIM1->SR &= ~TIM_IT_CC2;                     // clear the timer interrupt bit
}

void TIM2_IRQHandler(void)
   valid=1; // enable output after the first vertical blanking period after reboot
   vline=0; // reset the line counter
   TIM2->SR &= ~TIM_IT_CC2; // clear the timer interrupt bit
}
void DMA1_Stream5_IRQHandler(void)
{
   DMA1->HIFCR DMA_HIFCR_CHTIF5|DMA_HIFCR_CFEIF5|DMA_HIFCR_CTEIF5|DMA_HIFCR_CDMEIF5; //clear any DMA interrupt flags except end of transfer
   if(DMA1->HISR & DMA_HISR_TCIF5) {// If the interrupt is end of transfer
       DMA1->HIFCR = DMA_HIFCR_CTCIF5; //clear the end of transfer interrupt flag
       DMA1_Stream5->CR &= ~DMA_SxCR_EN; // disable the stream
       DMA1_Stream5->M0AR=(uint32_t)&fb[vline][0]; //point DMA to the next line
       vline++; //increment the line counter
       if(vline>=480) vline=480; //if in frame blanking just replay a blank line
   }
}